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dc.creatorAcevedo Patiño, Óscar
dc.creatorKagaris D.
dc.date.accessioned2020-03-26T16:32:44Z
dc.date.available2020-03-26T16:32:44Z
dc.date.issued2016
dc.identifier.citationIEEE Transactions on Computers; Vol. 65, Núm. 2; pp. 664-669
dc.identifier.issn00189340
dc.identifier.urihttps://hdl.handle.net/20.500.12585/8992
dc.description.abstractIn built-in test pattern generation and test set compression, an LFSR is usually employed as the on-chip generator with an arbitrarily selected characteristic polynomial of degree equal, according to a popular rule, to Smax+20, where Smax is the maximum number of specified bits in any test cube of the test set. By fixing the polynomial a priori a linear system only needs to be solved to compute the required LFSR initial states (seeds) to generate the target test cubes, but the disadvantage is that the polynomial degree (length of the LFSR and seed bit size) may be too large and the fault coverage cannot be guaranteed. In this paper we address the problem of computing a polynomial of small degree directly from the given test set without having to solve multiple non-linear systems and fixing a priori the polynomial degree. The proposed method uses an adaptation of the Berlekamp-Massey algorithm and the Sidorenko-Bossert theorem to perform the computation. In addition, the method guarantees (by design) that all the test cubes in the given test set are generated, thereby achieving 100% coverage, which cannot be guaranteed under the 'trial-and-error' Smax+20 rule. Experimental results verify the advantages that the proposed methodology offers in terms of reduced polynomial degree and 100% coverage. © 1968-2012 IEEE.eng
dc.format.mediumRecurso electrónico
dc.format.mimetypeapplication/pdf
dc.language.isoeng
dc.publisherIEEE Computer Society
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/
dc.sourcehttps://www.scopus.com/inward/record.uri?eid=2-s2.0-84962090065&doi=10.1109%2fTC.2015.2428697&partnerID=40&md5=d8909b99a8d0de0e0b965b6fd72ea7f0
dc.titleOn the computation of LFSR characteristic polynomials for built-in deterministic test pattern generation
dcterms.bibliographicCitationAcevedo, O., Kagaris, D., Using the Berlekamp-Massey algorithm to obtain LFSR characteristic polynomials for TPG (2012) Proc. IEEE Int. Symp. Defect Fault Tolerance VLSI Nanotechnol. Syst, pp. 233-238
dcterms.bibliographicCitationBakshi, D., Hsiao, M.S., LFSR seed computation, and reduction using SMT-based fault-chaining (2013) Proc. Des., Autom. Test Eur. Conf. Exhib, pp. 1071-1076
dcterms.bibliographicCitationBardell, P.H., McAnney, W.H., Savir, J., (1987) Built-In Test for VLSI: Pseudorandom Techniques, , New York NY USA Wiley
dcterms.bibliographicCitationFarebrother, R.W., (1988) Linear Least Squares Computations, , New York NY USA Marcel Dekker
dcterms.bibliographicCitationGustavson, F.G., Analysis of the Berlekamp-Massey linear feedback shiftregister synthesis algorithm (1976) IBM J. Res. Develop, 20 (3), pp. 204-212. , May
dcterms.bibliographicCitationHellebrand, S., Tarnick, S., Rajski, J., Courtois, B., Generation of vector patterns through reseeding of multiple-polynomial linear feedback shift register (1992) Proc. Int. Test Conf, pp. 120-129
dcterms.bibliographicCitationHuang, L.-R., Jou, J.-Y., Kuo, S.-Y., Gauss-elimination-based generation of multiple seed-polynomial pairs for LFSR (1997) IEEE Trans. Comput.-Aided Des. Integrated Circuits Syst, 16 (9), pp. 1015-1024. , Sep
dcterms.bibliographicCitationKalligeros, E., Kavousianos, X., Nikolos, D., Multiphase BIST A new reseeding technique for high test-data compression (2004) IEEE Trans. Comput.-Aided Des. Integrated Circuits Syst, 23 (10), pp. 1429-1446. , Oct
dcterms.bibliographicCitationKavousianos, X., Tenentes, V., Chakrabarty, K., Kalligeros, E., Defectoriented LFSR reseeding to target unmodeled defects using stuck-at test sets (2011) IEEE Trans. Very Large Scale Integration Syst, 19 (12), pp. 2330-2335. , Dec
dcterms.bibliographicCitationKim, H.-S., Kang, S., Increasing encoding efficiency of LFSR reseedingbased test compression (2006) IEEE Trans. Comput.-Aided Des. Integrated Circuits Syst, 25 (5), pp. 913-917. , May
dcterms.bibliographicCitationKoenemann, B., LFSR-coded test patterns for scan designs (1991) Proc. Eur. Test Conf, pp. 237-242
dcterms.bibliographicCitationKongtim, P., Reungpeerakul, T., Parallel LFSR reseeding with selection register for mixed-mode BIST (2010) Proc. IEEE Asian Test Symp, pp. 153-158
dcterms.bibliographicCitationKoutsoupia, M., Kalligeros, E., Kavousianos, X., Nikolos, D., LFSRbased test-data compression with self-stoppable seeds (2009) Proc. Des., Autom. Test Eur. Conf. Exhib, pp. 1482-1487
dcterms.bibliographicCitationKrishna, C.V., Jas, A., Touba, N.A., Test vector encoding using partial LFSR reseeding (2001) Proc. Int. Test Conf, pp. 885-893
dcterms.bibliographicCitationKrishna, C.V., Touba, N.A., Reducing test data volume using LFSR reseeding with seed compression (2002) Proc. Int. Test Conf, pp. 321-330
dcterms.bibliographicCitationLee, J., Touba, N.A., LFSR-reseeding scheme achieving low-power dissipation during test (2007) IEEE Trans. Comput.-Aided Des. Integrated Circuits Syst, 26 (2), pp. 396-401. , Feb
dcterms.bibliographicCitationLee, L.-J., Tseng, W.-D., Yang, W.-T., Dual-LFSR reseeding for low power testing (2012) Proc. Int. Workshop Microprocessor Test Verification, pp. 30-34
dcterms.bibliographicCitationLien, W.-C., Lee, K.-J., Hsieh, T.-Y., Chakrabarty, K., A new LFSR reseeding scheme via internal response feedback (2013) Proc. IEEE Asian Test Symp, pp. 97-102
dcterms.bibliographicCitationLien, W.-C., Lee, K.-J., Hsieh, T.-Y., A test-per-clock LFSR reseeding algorithm for concurrent reduction on test sequence length, and test data volume (2012) Proc. IEEE Asian Test Symp, pp. 278-283
dcterms.bibliographicCitationMassey, J., Shift-register synthesis, and BCH decoding (1969) IEEE Trans. Inf. Theory, 15 (1), pp. 122-127
dcterms.bibliographicCitationRajski, J., Tyszer, J., Primitive polynomials over GF(2) of degree up to 660 with uniformly distributed coefficients (2003) J. Electron. Testing, 19 (6), pp. 645-657
dcterms.bibliographicCitationSidorenko, V.R., Bossert, M., Synthesizing all linearized shift-registers of the minimal or required length (2010) Proc. Int. ITG Conf. Source, and Channel Coding, pp. 1-6
dcterms.bibliographicCitationSouza, C.P., Assis, F.M., Freire, R.C.S., Mixed test pattern generation using a single parallel LFSR (2006) Proc. IEEE Instrumentation Measurement Technol. Conf, pp. 1114-1118
dcterms.bibliographicCitationYilmaz, M., Chakrabarty, K., Seed selection in LFSR-reseeding-based test compression for the detection of small-delay defects (2009) Proc. Des., Autom. Test Eur. Conf. Exhib, pp. 1488-1493
dcterms.bibliographicCitationWang, L.-T., Chang, Y.-W., Cheng, K.-T., (2009) Electronic Design Automation Syn Thesis, Verification, and Test, , Burlington, MA, USA: Morgan-Kaufmann
dcterms.bibliographicCitationWang, Z., Fang, H., Chakrabarty, K., Bienek, M., Deviation-based LFSR reseeding for test-data compression (2009) IEEE Trans. Comput.-Aided Des. Integrated Circuits Syst, 28 (2), pp. 259-271. , Feb
datacite.rightshttp://purl.org/coar/access_right/c_16ec
oaire.resourceTypehttp://purl.org/coar/resource_type/c_6501
oaire.versionhttp://purl.org/coar/version/c_970fb48d4fbd8a85
dc.type.driverinfo:eu-repo/semantics/article
dc.type.hasversioninfo:eu-repo/semantics/publishedVersion
dc.identifier.doi10.1109/TC.2015.2428697
dc.subject.keywordsAlgorithm design and analysis
dc.subject.keywordsLinear systems
dc.subject.keywordsMathematical model
dc.subject.keywordsPolynomials
dc.subject.keywordsTest pattern generators
dc.subject.keywordsUpper bound
dc.subject.keywordsComputation theory
dc.subject.keywordsData compression
dc.subject.keywordsGeometry
dc.subject.keywordsLinear systems
dc.subject.keywordsMathematical models
dc.subject.keywordsAlgorithm design and analysis
dc.subject.keywordsBerlekamp-Massey algorithm
dc.subject.keywordsCharacteristic polynomials
dc.subject.keywordsDeterministic test pattern
dc.subject.keywordsPolynomial degree
dc.subject.keywordsTest pattern generator
dc.subject.keywordsTest-set compression
dc.subject.keywordsUpper bound
dc.subject.keywordsPolynomials
dc.rights.accessrightsinfo:eu-repo/semantics/restrictedAccess
dc.rights.ccAtribución-NoComercial 4.0 Internacional
dc.identifier.instnameUniversidad Tecnológica de Bolívar
dc.identifier.reponameRepositorio UTB
dc.type.spaArtículo
dc.identifier.orcid57197327858
dc.identifier.orcid7004389110


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